Keynote Talks

 

Dr. Tsung-Yung Jonathan Chang Fellow/Senior Director at TSMC, Taiwan Semiconductors and Test in Artificial Intelligence Era Abstract: Since their inception in the 20th century, semiconductors have played a pivotal role in rapidly enhancing human life. The development of personal computers, the internet, mobile devices, and high-performance computing (HPC) servers has brought immense computing power and connectivity into everyday existence. As we transition into the Artificial Intelligence (AI) era, advanced semiconductor technologies are crucial enablers, providing the necessary computing capabilities, memory capacity, and data transfer bandwidth. Innovations such as FinFET, GAA nanosheet transistors, and 3D stacking are at the forefront of this technological evolution. Additionally, new memories like MRAM, RRAM, and specialized memory IP, including compute-in-memory, are emerging to significantly improve power efficiency in AI and other applications.

As semiconductor products become increasingly vital for automotive safety, autonomous systems and AI applications, the need for novel test and design-for-test techniques is paramount to maintain quality and reliability amidst evolving device architectures and packaging methods. The industry faces significant challenges, such as integrating new materials and balancing enhanced performance with reduced power consumption. Overcoming these hurdles requires collaboration between industry and academia to foster innovative solutions, improve fault modeling, and utilize machine learning for failure prediction. Additionally, investing in advanced manufacturing and testing infrastructure is essential to propel next-generation semiconductor devices forward and sustain the momentum of the AI revolution.

Bio: Dr. Tsung-Yung Jonathan Chang is a TSMC Fellow and Senior Director leading memory IP development at TSMC. He is responsible for SRAM DTCO and memory IP development for advance technology nodes. Before joining TSMC, Dr. Chang was a principal engineer at Intel responsible for cache development for Enterprise server processors. He received B.S. degree from National Taiwan University, and M.S. and Ph.D. from Stanford University, all in electrical engineering. Dr. Chang is a fellow of IEEE, had served as the memory subcommittee chair from for ISSCC, TPC members of ISSCC, VLSI, associate and guest editors of Journal of Solid-State Circuits, and associate editor of IEEE Trans on VLSI. Dr. Chang has published more than 90 technical papers in IEEE conferences and journals and held 25 patents in embedded memory design.

Prof. Robert Wille Full Professor and Vice Dean for Research at TU Munich, Germany, and Chief Scientific Officer at the Software Competence Center Hagenberg GmbH, Austria Fault-Tolerant Quantum Computing: Why the ETS Community Should Get Involved! Abstract: Quantum computing holds immense promise for revolutionizing various fields with its unparalleled computational power. However, the inherent susceptibility of quantum systems to errors necessitates fault-tolerant design principles to ensure reliable operation. As we transition from Noisy Intermediate-Scale Quantum (NISQ) systems, where errors are tolerated, to Fault-Tolerant Quantum Computing (FTQC), the development of efficient fault-tolerant algorithms becomes crucial. This keynote will provide an overview of the current state of quantum computing and outline the challenges in making it fault-tolerant. The inability to clone information, the destruction of information after measurement, and high error rates that quickly turn computations into noise require significant expertise and experience to address.

The ETS community is perfectly equipped for this challenge and should get involved in efforts to overcome these obstacles.

Bio: For more than 15 years, Prof. Robert Wille is working on topics in the domain of quantum computing and successfully established design automation concepts in this domain. The impact of his work is reflected by numerous awards such as Best Paper Awards, e.g., at TCAD and ICCAD, a DAC Under-40 Innovator Award, a Google Research Award, etc., collaborations with numerous industrial partners in this domain, as well as his involvement in prestigious projects and initiatives, e.g., within the scheme of an ERC Consolidator Grant or the comprehensive quantum computing initiative of the Munich Quantum Valley. He published more than 400 papers and served in editorial boards as well as program committees of numerous journals/conferences.

 

Dr. Sreejit Chakravarty IEEE Fellow and Distinguished Engineer at Ampere Systems, USA Rethinking Silicon Test to reduce DPPM and Silen Data Corruption Abstract: Current SoC manufacturing testing uses a combination of structural and functional tests to meet product quality goals. This approach to manufacturing testing is falling apart due to the increase in data center SoCs as well as the scaling of data centers. In this talk we will highlight some of the weaknesses of the current manufacturing test paradigm and discuss areas that need further investigation. Bio: Dr. Sreejit Chakravarty is an IEEE Fellow, a highly recognized Researcher, Inventor, and a Distinguished Engineering Leader, with extensive industry and academic experience. He is currently a Distinguished Engineer at Ampere Computing, Santa Clara, CA, USA where he drives strategic initiatives for product quality. Prior to this he had over 25 years of industry experience as a Principal Engineer with Intel Corporation and Distinguished Engineer at LSI and AVAGO (now Broadcom).

He started his career in academia as an Associate professor of Computer Science, at The State University of New York at Buffalo, where his work was funded by multiple National Science Foundation Grants.
He has architected innovative solutions across the entire silicon life cycle spanning Silicon Quality and Reliability (RAS, Functional Safety and Silent Data Errors); and subsequently drove them from concept to product intercept.
He has published 1 book, authored 145+ IEEE papers and has 23 issued US patents. He has served in various capacity at numerous IEEE conferences and delivered multiple keynote addresses, the latest being at the IEEE Asian Test Symposium, 2023. He has mentored research at several universities like Princeton, USC, UIUC, etc. For his professional work he has been recognized as an IEEE Fellow and SUNY Distinguished Alumni. He currently chairs the IEEE P3405 Work Group on Chiplet Interconnect Test and Repair, which aims to standardize the test and repair of chiplet interconnects which will lay the foundation to realize the chiplet revolution.