Regular/Research Papers
Download Call for Papers [PDF]
Guidelines
Each submitted paper should be a complete PDF manuscript, up to six (6) pages (inclusive of all figures, tables, and bibliography) in a standard IEEE format: A4 pages, two columns, single spaced, 10 points Times New Roman font. IEEE template and guidelines can be found [here]. Papers not compliant with the IEEE template or exceeding the page limit will be returned without review!
ETS implements a single-blind review process (i.e. the authors do not know who the reviewers are, but the reviewers know who the authors are). Therefore, submissions should not be anonymized.
Papers identified as multiple submissions with respect to other conferences and/or journals will also be rejected. Authors are expected to follow the IEEE Submission and Peer Review Policies, including the latest Policy on plagiarism as well as the Guidelines for AI generated text, all of which can be found [here].
A submission of a scientific paper is considered as a commitment that, upon acceptance, authors will submit their camera-ready version for inclusion in the formal proceedings and will present the paper (or the poster) at the symposium. Full 6-page papers to be presented as an in-person oral talk, while a short 4-page paper implies a poster presentation. ETS reserves the right to remove from IEEE Xplore papers and posters that have not been properly presented at the symposium.
Key Dates for the Regular/Research Papers
- Submission of title, abstract, authors: December 1, December 9, 2024
- Full paper submission: December 8, December 15, 2024 (AOE - anywhere on Earth)
- Notification of acceptance: February 14, 2025
- Camera-ready manuscript: March 14, 2025
- Author registration: March 31, 2025
Submission Website
Submissions should be made electronically as a single PDF file. Click [here] to submit your paper.
Publications
ETS'25 will produce electronic formal proceedings - with ISBN number, and to be indexed in the IEEE Xplore digital library and other bibliographical search engines. Scientific papers can be accepted for:
- oral presentation: you will be asked to prepare a final 6-page manuscript for inclusion in the formal proceedings;
- poster presentation: in this case a 4-page paper will be included in the formal proceedings.
The formal proceedings will contain the PDF files of all accepted full papers and posters.
The Best Paper Award of ETS’25 will be presented at ETS’26.
Topic Areas for Submission
Below you can find the list of topic areas (not limited to) for ETS’25.
- T1 – Dependable AI and AI for Testing AI/ML is thriving across numerous applications and we are only at the beginning of the revolution. Not surprisingly, AI/ML is gaining popularity for solving dependability and testing problems for ICs. In parallel, we need to address the problem of dependability and testing of emerging AI hardware accelerators. This topic considers fault modeling, structural testing, functional testing, on-line test, reliability, fault tolerance and functional safety, all for AI/ML hardware. Also, it considers the application of AI/ML in IC manufacturing testing, reliability, fault diagnosis and failure analysis, on-line testing, anomaly detection, and functional safety.
- T2 – Functional Safety, Fault Tolerance and Reliability Functional safety (FuSa) and reliability are essential aspects of modern electronic systems, especially in automotive, aerospace, medical, and industrial domains. These systems require advanced design and test methods to ensure their correct, secure, and dependable operation in the field. Topics of interest include: dependability enforcement, defense mechanisms, design for reliability, safety insurance, fault detection or tolerance techniques, online testing, self-repair, robustness assessment methods, fault injection, and yield analysis.
- T3 – Methods for Emerging Technologies and Architectures Until now, incremental improvements in device technology and computer architecture make the development of high-performance applications possible. However, limitations on transistor miniaturization and today’s emerging applications requirements pose challenges with respect to CMOS technology scaling and von Neumann architecture. A paradigm shift is needed to enable new performance breakthroughs, such as non-CMOS-based technology as well as novel processing and computing paradigms, leading to new defect mechanisms, faulty behaviors and eventually novel DfT techniques. This topic considers aspects related to test and reliability for: emerging memories; in-memory computing; neuromorphic architectures; approximate circuits; photonic devices and architectures; quantum and reversible circuits and architectures.
- T4 – Security and Trust This topic includes methods, design solutions, and tools aimed at enhancing security and trust, with a particular focus on dependability issues encompassing test, reliability, and safety. More in particular, we consider papers targeting Test and Security (discussing security issues in test and the testing of secure devices), Fault Attacks and Countermeasures (fault-injection equipment, fault-based cryptanalysis, case studies), Dependability of Secure Circuits (including security primitives such as PUFs and TRNGs), Trust Issues and Countermeasures (hardware Trojans, reverse engineering, and supply chain attacks), Side Channel Analysis and Countermeasures (power attacks, timing attacks, microarchitectural attacks, covert channels).
- T5 – Test and Reliability for Analog, Mixed-Signal, and RF Despite many years of research efforts, Analog, Mixed-Signal and RF test remains highly circuit-specific. The complexity of the problem stems from both the diversity of performance specifications and the sensitivity to any change in the signal path. However, AMS-RF researchers are undeterred, and this topic will bring together their latest advances. Topics include test and reliability in analogue and mixed-signal circuits, high-speed digital circuits, MEMS sensors and RF circuits.
- T6 – DFT, Test Access Standards and Test Application Design for Testability (DFT) solutions are needed to provide the circuit access required to achieve ultra-low defect levels at manufacturing and enable the detection of new failures later in the field. Updated standards for secure and effective test are also needed to ensure interoperability. This topic considers all hardware aspects of design for test for circuits and system architectures such as NoC, SoC, classical 2-D, 2.5-D and 3-D test and chiplets. We cover among others built-in self-test, scan design, test interfaces, and online monitoring, as well as all test and test access standards and their applications.
- T7 – Validation, Verification, and Debug Methodologies and tools for validation, verification and debug of ICs, embedded hardware and software, and cyber-physical systems, by exploiting formal, semi-formal and dynamic approaches, with or without the use of artificial intelligence. Topics include: testbench and assertion generation and qualification; fault/mutant modeling and simulation; checker synthesis and optimization; multi-domain and mixed-critical validation and verification techniques; pre- and post-silicon debugging solutions; security verification and detection of vulnerabilities; formal verification methods and core algorithm techniques supporting formal verification; acceleration-driven and emulation-based approaches for verification; verification and validation of safety mechanisms.
- T8 – Test Generation, Fault Modeling & Simulation, Diagnosis Test generation, fault modeling/fault simulation and diagnosis techniques across various abstraction levels, e.g. cell-aware, gate-level, system-level, as well as for different fault models, e.g. traditional, defect-oriented and transient. Sub-topics include: adaptive testing; ATPG; defect-oriented testing; fault simulation; transient faults; system-level test; solving techniques; delay test; efficiency/effectiveness; feedback & iterative improvement; pre- and post-silicon diagnosis.
Contact Information
Program Chairs
- Matteo Sonza Reorda, Politecnico di Torino, matteo.sonzareorda@polito.it
- Arnaud Virazel, LIRMM - University of Montpellier, arnaud.virazel@lirmm.fr