The 30^th IEEE European Test Symposium (ETS) is Europe's premier forum dedicated to presenting and discussing scientific results, emerging ideas, hot topics and new trends, as well as industrial case-studies and applications in the area of electronic-based circuits and systems testing, reliability, safety, security and validation.

This year we will celebrate the anniversary 30^th edition of ETS!

In 2025, the symposium is organized by Tallinn University of Technology (TalTech), which co-sponsors the event jointly with the IEEE Council on Electronic Design Automation (CEDA). It will take place in Swissotel in Tallinn. The city is known for the picturesque Old Town with its medieval architecture.

Publications

ETS'25 will produce Formal Proceedings of scientific papers with ISBN number that will be indexed by the IEEE Xplore Digital Library. Also, an Informal Digest will collect contributions in other categories with an open access on-line archiving option.

In addition to regular Research Papers, Keynotes, Special Sessions, Panels, and Embedded Tutorials, ETS’2025 also features papers/highlights/demos and vendor sessions from the industry, as well as a rich set of student-related activities including a PhD Forum and a PhD Thesis Competition. ETS’2025 will be the major event of the European Test Week that also includes the Test Spring School (TSS) and Fringe Workshops.

Submissions

ETS'25 seeks original, unpublished contributions of the following types:

• Scientific Papers for the Formal Proceedings, presenting novel and complete research work
• Industrial Contributions presenting results, highlights, or demos for Informal Proceedings
• Student Contributions for the PhD Forum and McCluskey Thesis Contest
• Proposals for Panels, Embedded Tutorials, Special Sessions and Fringe Workshops

The areas of interest include (but are not limited to) the following topics:

3D IC and SiP Test Analog, Mixed-signal and RF Test Approximate Circuit Testing ATE Hardware and Software Automatic Test Generation Automotive and Avionics Test Board Test and Diagnosis Built-In Self-Test Current-Based Test Defect-Based Test Delay and Performance Test Dependability Design for Test DfX (Design for Manufacturing, Reliability, Yield, etc.) Diagnosis and Silicon Debug Economics of Test

Extra-Functional Aspects Failure Analysis Fault Modeling Fault Simulation Fault Tolerance Functional Safety Hardware Security Heterogeneous and Emerging Architectures High-Speed I/0 Test IoT and CPS Dependability Low-Power Test Machine Learning and Test Memory Test and Repair Microsystems / MEMS / Sensors Test On-line Test

Power- / Thermal-Aware Test Processor Test (Multi-Core, GPU, CPU, Neuromorphic, etc.) Security-Test Trade-offs Self-X (Awareness, Repair, Test, etc.) Signal Integrity Test SoC and NoC Test Standards in Test Test for Reversible and Quantum Circuits Test of Reconfigurable Systems (FPGA, CPLD, etc.) Test, Reliability and Security of Emerging Technologies Trojan Detection Verification and Validation Yield Analysis and Enhancement

 

Contacts

General Chairs

• Artur Jutman, Testonica, artur@testonica.com
• Jaan Raik, TalTech, jaan.raik@taltech.ee

Program Chairs

• Matteo Sonza Reorda, Politecnico di Torino, matteo.sonzareorda@polito.it
• Arnaud Virazel, LIRMM - University of Montpellier, arnaud.virazel@lirmm.fr