ETS2025 Tallinn, Estonia
30th IEEE European Test Symposium
May 26 - 30, 2025
Tallinn, ESTONIA

Preliminary Program

 

ETS25 Preliminary technical program

 

Tuesday, May 27

8.30 – 9.00

Opening session

 

9.00 – 9.45

Keynote talk #1

Tsung-Yung Jonathan CHANG, “Semiconductors and Test in Artificial Intelligence Era

 

9.45 – 10.30

Coffee-break and Scientific Posters session #1

 

Paper #20         Holistic Memory DFT Partitioning Using a Convolution-Based Algorithm,
Olivier ROMAIN, Wojciech GIERSZAL, Luc ROMAIN, Artur POGIEL

Paper #23         A UCIe Compatible Repair Scheme for the Clustered Faults in the Hexagonal Array of Interconnect Lanes,
Zhaohong LIN, Xiaole CUI, Juncheng PU, Huan YANG

Paper #45         Modeling and Analysis of Aging Impact on SRAM PUFs for Advanced FinFET Technology Nodes,
Shayesteh MASOUMIAN, Roel MAES, Noemie BERINGUIER-BOHER, Karthik KENI YERRISWAMY, Geert-Jan SCHRIJEN, Said HAMDIOUI, Mottaqiallah TAOUIL

Paper #56         Pulsed Electromagnetic Fault Injection Attack on Ring Oscillator-based PUFs in FPGAs,
Sami EL AMRAOUI, Aghiles DOUADI, Regis LEVEUGLE, Paolo MAISTRI

Paper #78         Multi-Context Execution on a RISC-V Core for Mixed-Criticality System,
Leonardo FAZZINI, Giacomo VALENTE, Fabio FEDERICI, Matthew CORBETT, Tania DI MASCIO

Paper #50         Analysis and Mitigation of Radiation Effects in SRAM-based Register Files,
Zhe ZHANG, Surendra HEMARAM, Mahta MAYAHINIA, Christian WEIS, Norbert WEHN, Mehdi TAHOORI, Sani NASSIF, Grigor TSHAGHARYAN, Gurgen HARUTYUNYAN, Yervant ZORIAN

Paper #11         Towards Understanding of System-Level Test-Unique Fails,
Nourhan ELHAMAWY, Jens ANDERS, Ilia POLIAN, Matthias SAUER

Paper #76         Synergistic Built-In ECC Repair (BIER) Technique for Enhancing Yield and Reliability of Flash Memory,
Shyue-Kung LU

 

10.30 – 12.00

Regular session #1 – Test and diagnosis

 

Paper #13         Identification of Failing Flip-Flops with Triangular Test Response Compaction, Jerzy TYSZER, Grzegorz MRUGALSKI, Janusz RAJSKI, Maciej TRAWKA

Paper #53         Automated Test Equipment Drift Characterization Based on Gauge Repeatability and Reproducibility,           
Anand VENKATACHALAM, Ernst ADERHOLZ, Matthias SAUER, Simon SCHWEIZER, Matthias WERNER, Ilia POLIAN

Paper #55         Automatic Test Pattern Generation for Printed Neuromorphic Circuits, 
Tara GHESHLAGHI, Priyanjana PAL, Alexander STUDT, Michael HEFENBROCK, Michael BEIGL, Mehdi TAHOORI

 

10.30 – 12.00

Industrial session #1 – Reliability: automotive and beyond automotive

 

Paper #149      Optimized MBIST-Based MRAM Testing for Automotive MCUs to Achieve Superior Performance and Quality Assurance
Vinayak Bharat NAIK, Gregory BILLUS, Amit Kumar SHUKLA, Andre VOGEL, Veit KRIEGERSTEIN, Patrick SCHARF, Venkata Siva KOMMA, Johannes MUELLER, Thomas MERBETH, Ralf FLEMMING, Ingolf LORENZ, Muthu Kumaran NAMBI, Ee Ee YEOH, Chaya HEMAVATHI, Siddharth GUPTA, Yentsai HUANG, Sushma SAMBATUR, Joerg WINKLER, Tom ANDRE, Shane HOLLMER, Steven SOSS, Jongsin YUN, Wei ZOU, Harshitha KODALI, Luc ROMAIN, Albert AU, Lori SCHRAMM, Martin KEIM

Paper #150      Soft Error Resiliency Evaluation for Telum II® processor core
Matthias PFLANZ, Tripta GUPTA

Paper #133      Silent Data Corruption and Signal Integrity Test, How to Achieve 0ppm?
Peter POECHMUELLER, Chenyu FANG

 

10.30 – 12.00

Special session #1 - Dependable Neuromorphic Computing-in-Memory Architectures

Organizer: F. MERCHANT

Speakers: C. WENGER, M. GOMONY, S. KVATINSKY, V. RANA

 

 

12.00 – 13.15

Lunch

 

13.15 – 14.45

Regular session #2 – Reliability and AI

Paper #100      Non-Uniform Error Correction for Hyperdimensional Computing Edge Accelerators,
Mahboobe SADEGHIPOURRUDSARI, Surendra HEMARAM, Mehdi TAHOORI

Paper #22         An Integrated Framework for Aging Analysis Based on an Age-Aware Cell Library, Amirmahdi JOUDI, Negin SAFARI, Fatemeh MOHAMMADZADEH, katayoon BASHARKHAH, Fatemeh SHEIKH SHOAEI, Zainalabedin NAVABI

Paper #92         FastGDBN: A GPU-Accelerated DNN for Identifying Good Dies in Bad Neighborhoods,
Yu HENG TSAO, Yu Guang CHEN

 

13.15 – 14.45

Industrial session #2 – Analog test: modelling, coverage and standards

Paper #137      Efficient Noise Injection Methodology for Sample and Hold Circuits in AMS Behavioral Models
Thorben SCHEY, Khaled KAROONLATIFI, Michael WEYRICH, Andrey MOROZOV

Paper #158      Fault Grading at the Analog-Digital interface in AMS integrated circuit
Iacopo GUGLIELMINETTI, Michelangelo GROSSO, Riccardo CANTORO

Paper #144      Integrating Analog Resource Control in Digital Test Patterns with IEEE Standard
Anthony COYETTE, Cahyo PRIMAWIDODO, Ric DOKKEN

 

13.15 – 14.45

Special session #2 - Printed and Flexible Electronics: From Design to Test

Organizer: M. TAHOORI

Speakers: M. TAHOORI, Emre OZER, G. ZERVAKIS

 

14.45 – 15.30

Coffee break, PhD forum and McCluskey contest posters

 

15.30 – 17.00

Regular session #3 – Security solutions

Paper #64         Early Result Capture: Racing Conditions in Pipeline due to Clock Glitches,
Roua BOULIFA, Giorgio DI NATALE, Paolo MAISTRI

Paper #2            Multi Coefficient CPA on a Black Box Hardware Implementation of CRYSTALS-Kyber,
Tarick WELLING, Maël GAY, Ilia POLIAN

Paper #41         Machine Learning-Assisted Side-Channel Analysis for Software Integrity Verification,
Niklas LINDSKOG, Håkan ENGLUND, Jakob STERNBY, Elena DUBROVA

 

15.30 – 17.00

Industrial session #3 – Panel

Chiplet and advanced packaging devices: what are we missing to test them effectively?

 

15.30 – 17.00

Special session #3

Good, Bad, & Ugly in Quantum Computing: Computational Power, Intrinsic Noise & Transient Faults,
Organizers: P. RECH, E. GIUSTO

Speakers: O. DI MATTEO, A. VEPSALAINEN, F. MANTEGAZZINI, A. CILARDO

 

17.00 – 18.00

ETSteams Forum

 

18.00 – 19.30

Panel session #1 – 30th year ETS anniversary

 

Organizer: M. JENIHHIN

 


Wednesday, May 28

8.30 – 9.15

Keynote talk #2

Robert WILLE, Fault-Tolerant Quantum Computing: Why the ETS Community Should Get Involved!

 

9.15 – 10.45

Regular session #4 – Fault attacks and security risks

Paper #67         BISSEL: Built-In Self Security via Embedded Sensors for Reproducible Side-Channel Leakage Assessment,
Md Toufiq Hasan ANIK, Hasin Ishraq REEFAT, Jean-Luc DANGER, Sylvain GUILLEY, Naghmeh KARIMI

Paper #9            Security Risks in AI Accelerators: Detecting RTL Vulnerabilities to Model Theft with Formal Verification,
Mohamed SHELKAMY ALI, Lucas DEUTSCHMANN, Johannes MüLLER, Anna Lena DUQUE ANTóN, Mohammad R. FADIHEH, Dominik STOFFEL, Wolfgang KUNZ

Paper #12         Securing Reconfigurable Scan Networks Against Data Sniffing and Data Alteration Attacks,
Joel ÅHLUND, Markus TöRMäNEN, Pamela SVENSSON, Mikael KERTTU, Torbjörn MåNEFJORD, Erik LARSSON

 

9.15 – 10.45

Industrial session #4 – Test solutions: methods and tools

Paper #135      Enhancing Bluetooth ATE Testing Efficiency
MANIBHARATH NERAVATI, Pragya NAHAR

Paper #152      High-Speed Loopback Applications by Utilizing a Differential DP3T MEMS Switch
Stewart YANG, Ian BURKE

 

9.15 – 10.45

Special session #4 - Self-Aware Silicon: Enhancing Lifecycle Management with Intelligent Testing & Data Insights

Orghanizer: S. HUHN

Speakers: F. VARGAS, H. AMROUCH, D. TILLE

 

10.45 – 11.00

Coffee break

 

11.00 – 12.30

Regular session #5 – Reliability and LLMs

Paper #52         LLM-aided Test Generation for Custom Neural Network Hardware Accelerators, Federico PECCIA, Tobias HALD, Oliver BRINGMANN

Paper #32         Confidence Driven Compact Testing of Compute-in-Memory Based Language Models,
Anurup SAHA, Chandramouli AMARNATH, Kwondo MA, Abhijit CHATTERJEE

Paper #40         On the Fault Sensitivity of Natural Language Embeddings Computation,
Sumeet SAPKAL, Ussama ZAHID, Giulio GAMBARDELLA, Haralampos STRATIGOPOULOS, Brian CLERKIN

 

11.00 – 12.30

Industrial session #5 – Advanced packaging views: standards, probe and security

Paper #151      Testing Functional Interfaces And Complex PADs Within Multi-Die Packages With IEEE P3405
Anshuman CHANDRA, Nir SEVER, Martin KEIM

Paper #147      Eclipse Dynamic: An Integrated Probe Card for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Alessia GALLI, Riccardo VETTORI

Paper #141      Cocktail Security Scheme for Patching the Vulnerability of the Communication Bus in A Chiplet-Based IC
Jui-Hsien WANG, Zheng-Hao WANG, Shi-Yu HUANG, Chen CHI-KANG

 

11.00 – 12.30

Special session #5 - On the dependability of emerging neuromorphic accelerators for SNNs

Organizers: A. GEBREGIORGIS, T. SPYROU

Speakers: H. STRATIGOPOULOS, I. ALOUANI

 

12.30 – 14.00

Lunch

 

14.00 – 15.30

Panel session #2 - Chips Act in EU: where are we standing and what is next?

Organizer: S. HAMDIOUI

 

16.00 – 22.00

 

Social event

 

 

Thursday, May 29

8.30 – 9.15

Keynote talk #3

Sreejit CHAKRAVARTY, Rethinking Manufacturing Testing to address Silent Data Errors

 

9.15 – 10.15

Regular session #6 – RRAM testing

Paper #44         Structural Testing of a RRAM-based AI Accelerator Core,
Emmanouil Anastasios SERLIS, Hanzhi XUN, Mottaqiallah TAOUIL, Said HAMDIOUI, Moritz FIEBACK

Paper #83         In-Field Monitoring and Preventing Read Disturb Faults in RRAMs,
Hanzhi XUN, Moritz FIEBACK, Sicong YUAN, Changhao WANG, Erbing HUA, Leticia BOLZANI POEHLS, Hassen AZIZA, Riccardo CANTORO, Mottaqiallah TAOUIL, Said HAMDIOUI

 

9.15 – 10.15

Embedded tutorial #1 - Physical Unclonable Functions (PUFs): Foundations, Evaluation, and Testing for Secure Hardware Systems

Elena Ioana VATAJELU, Giorgio DI NATALE

 

9.15 – 10.15

Embedded tutorial #2 - Opportunities and Challenges in AI Computing with Chiplet Architectures: Integrating CMOS and Emerging Technologies for Future Innovations

Leticia Maria BOLZANI POEHLS, Hussam AMROUCH

 

10.15 – 11.00

Coffee-break and Scientific Posters session #2

 

Paper #15         MTMS: Age-Aware Multi-Task Multi-Layer Stacking for SSD Failure Prediction,
Zijun JING

Paper #43         Reliability Under Stress: The Impact of Localized Aging on RO-PUF Architectures in FPGAs,
Aghiles DOUADI, Elena Ioana VATAJELU, Paolo MAISTRI, David HELY, Vincent BEROULLE, Giorgio DI NATALE

Paper #60         Synthesizing 56 Gbps NRZ Test Signals Using FPGAs and SiGe Logic,
David KEEZER, Cao WANG, Shengbo LIU

Paper #93         FSMlock: Defending against Oracle-based Sequential Logic-Locking Attacks under Output-Corruption Requirements,
Ioannis STAVRINOS, Christos CHALAGIANNIS, Emmanouil KALLIGEROS

Paper #33         Silent Data Corruption: Root Causes in DRAM and Ways of Improving Semiconductor Test Quality Towards 0ppm,
Peter POECHMUELLER, Chenyu FANG

Paper #36         SiFFS: A Scalable in-Fault Functional Simulation Framework for Fault Criticality Analysis,
Haripriya R S, Naveen KOLLEPARA, Jaynarayan TUDU

Paper #49         Optimizing RO-PUFs: A Filtering Approach to Reliability and Entropy Trade-off,
Vasilii KULAGIN, Giorgio DI NATALE, Elena Ioana VATAJELU

Paper #82         Local Trimming Method for Enhancing the Read Reliability of STT-MRAMs,
JIN-FU LI, Pei-Yun LIN

Paper #104      Pin Electronics for Instrumentation and Automated Test Equipment: Challenges and Solutions,
Sandeep D'SOUZA, Matthew GETZ, Patrick SULLIVAN, Gerwin VELTINK, Paul VAN ULSEN

 

11.00 – 12.30

Regular session #7 - DfT and BIST solutions

Paper #25         Design-for-Test and Calibration for Silicon Photonics using Ring Resonators and Wavelength Division Multiplexing,
Pratishtha AGNIHOTRI, Lawrence SCHLITT, Priyank KALLA, Steve BLAIR

Paper #59         A Novel BIST Method for Multi-Port Register Files,
Andy CHEN, Vianney CHOSEROT, Munish KUMAR, Khushal GELDA, Shreyas DIXIT, Wei ZOU, Jongsin YUN, Harshitha KODALI, Albert AU, Lori SCHRAMM, Martin KEIM

Paper #72         MBIST-guided Reliability Improvement Scheme for SRAM-based Computation in Memory,
Sina BAKHTAVARI MAMAGHANI, Jongsin YUN, Martin KEIM, Mehdi TAHOORI

 

11.00 – 12.30

Industrial Session #6 – Probing: efficiency, technologies and test

Paper #138      AI-Assisted Framework for Real-Time Monitoring and Management of Probe Cards in Electrical Wafer Sort Applications
Mehdi BEJANI, Davide APPELLO, Marco MAURI, Simone TODARO, Stefano MARIANI

Paper #145      Performance improvement of IoT product wafer testing using MLO Probe card in ATE
W ALBAN IMMANUEL, W ALBAN HAYNSE IMMANUEL, JEY NITHYANANDAM

Paper #143      Multi-site Testing at Wafer Sort for Power Devices
Aseem SRIVASTAVA, Tom TRAN

 

11.00 – 12.30

Special Session #6 – Large Language Models for Verification, Testing and Design

Organizer: C. KUMAR JHA

Speakers: B. LI, S. GARG

 

12.30 – 14.00

Lunch

 

14.00 – 15.30

Regular session #8 - Advances on Chiplet testing and security

Paper #39         Extendable E2I-TEST for Chiplet-based Inter-die Interconnects,
Po-Yao CHUANG, Erik Jan MARINISSEN

Paper #74         DFT Techniques For Efficient 3D IC Interconnect Test For Chiplet and Multi-Die Package,
Anshuman CHANDRA, Chi-Chun YANG, Quoc PHAN, Martin KEIM

Paper #68         FLARE: Fault Attack Leveraging Address Reconfiguration Exploits in Multi-Tenant FPGAs                ,
Jayeeta CHAUDHURI, Hassan NASSAR, Dennis GNAD, Jörg HENKEL, Mehdi TAHOORI, Krishnendu CHAKRABARTY

 

14.00 – 15.30

Industrail session #7 - Diagnosis and verification

Paper #157      Improving Chain Diagnosis Resolution with Parallel Load Control Circuit
Yinxuan LYU

Paper #142      Building Asymmetric Partition Trees (APT) for Various Diagnosis Applications
Wu-Tung CHENG

Paper #116      A novel way to handle non-convergence of properties in formal verification of digital systems
Surinder SOOD, Nirmal JOSE, Kishan MUSHAR

 

15.30 – 16.00

 

Closing session